The present invention relates to a charge transfer device, and more particularly to a charge transfer device suitable for use for a charge transferring section of a high density solid-state image sensing device, for instance.
As a charge transfer device (CTD), there exists a charge coupled device (CCD) for transferring charges generated at pixels by controlling potentials generated in a semiconductor substrate.
FIG. 1 shows a most typical CCD of single-line read structure. In FIG. 1, pixels 601, a buried channel region 602 as the CCD register, a shift gate electrode 603 and two register transfer electrodes 604 and 605 are formed in a substrate. A great number of pixels 601 are formed one by one in a line at regular intervals, and each pixel 601 generates and accumulates a signal charge according to the intensity of incident light. The shift gate electrode 603 controls the charge transfer from the pixels 601 to the buried channel region 602. The register transfer electrodes 604 and 605 control the charge transfer on and along the buried channel region 602.
A drive pulse signal 6a is applied to the shift electrode 603; a drive pulse signal 6b is applied to the transfer electrode 604; and a drive pulse signal 6c is applied to the transfer electrode 605, respectively.
In operation, when a shift gate channel region under the shift gate electrode 603 in the substrate is turned on in response to the drive pulse signal 6a, the accumulated charges of the respective pixels 601 flow through the turned-on shift gate channel region into potential wells formed in the buried channel region 602 and under the two register transfer electrodes 604 and 605. Thereafter, the charges in the wells are transferred in sequence to an output circuit (not shown) when the drive pulse signals 6b and 6c are turned on or off alternately and reciprocally.
In the technical field of the above-mentioned CTD, the pixels are recently microminiaturized more and more into a higher density in the same way as with the case of other semiconductor devices. Therefore, when the pitch of the pixels is decreased in the CCD for higher density, the pitch of the potential wells (formed in the buried channel region 602 so as to function as register sections) arranged for the respective pixels and the register transfer electrodes 604 and 605 are also inevitably decreased, thus restricting the further microminiaturization of the CCD.
To overcome this problem, a CCD of multi-line read structure has been so far proposed such that the charge transfer from a great number of pixels to the buried channel region (potential wells) is divided or shared by a plurality of transfer register lines.
FIG. 2 shows a charge transfer device of two-line read structure, as the basic device of the multi-line read CCD. In FIG. 2, there are formed pixels 701, two buried channel regions 702 and 703 of the CCD register (referred to as a first RC (register channel) region 702 and a second RC region 703, respectively), a shift gate electrode 704, a transfer gate electrode 705 for controlling the charge transfer from the first RC region 702 to the second RC region 703 in a substrate. The transfer gate electrode 705 is arranged so as to face the alternate pixels.
Charges of a number of pixels 701 are once transferred to the first external RC region 702 by the shift gate electrode 704, and then the charges of the alternate pixels 701 are further transferred to the second RC region 703 by the transfer gate electrode 705. Thereafter, the charges in the first and second RC regions 702 and 703 are transferred to an output circuit (not shown), respectively.
FIG. 3 and FIGS. 4A and 4B are enlarged views showing the structure of the charge transfer device shown in FIG. 2, in which a two-layer poly silicon electrode structure is shown by use of the same reference numerals as with the case of the charge transfer device shown in FIG. 2.
In these drawings, a plurality of n-type pixels 701 and n-type first and second RC regions 702 and 703 are formed in a p-type substrate 801. Under transfer gate electrode 705, a transfer gate burying channel region 802 (referred to as TC region, hereinafter) is formed. The TC region 802 is composed of an n-type region 803 and n-type region 804, adjacent to each other. The n-type region 803 is adjacent to the first RC region 702. Further, under a shift gate region 704, an n-type shift gate channel region 805 (referred to as GC region, hereinafter) is formed.
Transfer control electrodes 806 to 809 are arranged on the first and second RC regions 702 and 703. A drive signal 8a as shown in FIG. 5C is applied to the transfer control electrodes 806 and 809, and a drive signal 8b as shown in FIG. 5D is applied to the transfer control electrodes 807 and 808. The charges on the first and second RC regions 702 and 703 are transferred to an output circuit by inverting the drive signals 8a and 8b alternately and reciprocally.
FIGS. 5A to 5D show a timing charge of these drive pulse signals 7a, 7b, 8a and 8b, respectively. Further, FIGS. 6A and 6B show two potential distributions at the cross sections as shown in FIG. 3.
The operation of the device as shown in FIG. 2 will be described hereinbelow with reference to these drawings. Further, the charges of the pixels 701 transferred from the first RC region 702 to the output circuit are referred to as charges e1, and the charges of the pixels 701 transferred from the second RC region 703 to the output circuit are referred to as charges e2, respectively.
With reference to FIGS. 3, 6A and 6B, at time point t1, the drive pulse signals 7a and 8a are both at an "H" level and the drive pulse signals 7b and 8b are both at a "L" level. Accordingly, the charges e1 and e2 of the pixels 701 are in the wells under the shift gate electrodes 704. Under these conditions, at time point t2, when the drive signal 7a changes to the "L" level, the charges e1 and e2 under the shift gate electrode 704 are transferred to the first RC region 702. Further, at time point t3, since the drive signal 8a is also changed to the "L" level, the charges e1 and e2 transferred to the first RC region 702 stand by thereat. From this time point, the transfer of only the charges e2 starts from the first RC (register channel) region 702 to the second RC (register channel) region 703.
First, at time point t4, since only the drive pulse signal 7b is at the "H" level, the TC (transfer channel) region 802 is turned on, so that the charges e2 in the first RC region 702 are transferred to the TC region 802. Next, at time point t5, since all the drive pulse signals are changed to the "L" level, the TC region 802 is turned off, so that the charges e2 in the TC region 802 are transferred to the second RC region 703 lower in potential than the TC region 802, thus completing the transfer of the charges e2 between the two RC regions 702 and 703.
Further, the charges e1 are kept remaining in the first RC region 702 between the time points t2 to t5. At the time point t6, since the drive pulse signal 8a changes to the "L" level and the drive pulse signal 8b changes to the "H" level, the charges e1 and e2 are all transferred from the regions under the electrodes 806 to the regions under the electrodes 807 and 808 in the first and second RC regions 702 and 703, respectively. Thereafter, whenever the drive pulse signals 8a and 8b are inverted alternately and reciprocally, the charges e1 and e2 are transferred to the output circuit on the first and second RC regions 702 and 703.
Further, FIG. 7 shows a conventional charge transfer device of two-line read and three-layer poly silicon electrodes structure, in which a first layer electrode is denoted by dot-dashed lines, a second layer electrode is denoted by dot-dot-dashed lines, and a third layer electrode is denoted by dashed lines, respectively.
In FIG. 7, electrodes C01 to C04 for constituting a CCD register portion, and an electrode C05 for constituting a transfer gate portion are all formed in a substrate. The electrode C01 and C03 are arranged on the first layer, the electrodes C02 and C04 are arranged on the second layer, and the electrode C05 is arranged on the third layer, respectively.
Further, in FIG. 7, a drive pulse signal Ca is applied to the electrodes C03 and C04 and a drive pulse signal Cb is applied to the electrodes C01 and C02, respectively to control the charges on the first and second RC regions 702 and 703.
In comparison between the devices shown in FIG. 3 and FIG. 7, a difference between the two is as follows: in the case of the charge transfer device shown in FIG. 3, the shapes of the electrodes 806 to 809 are such that both ends of the electrodes 806 to 809 are located on the same longitudinal position of the first and second RC regions 702 and 703, respectively. In other words, the charges on the first and second RC regions 702 and 703 are arranged at the same positions in the longitudinal transfer direction of the RC regions.
In contrast with this, in the case of the charge transfer device shown in FIG. 7, the shapes of the electrodes C01 to C04 are such that one portions of the electrodes C01 to C04 located on the first RC region 702 are offset by one pitch of the pixel 701 from other portionss of the same electrodes C01 to C04 located on the second RC region 703. Therefore, the charges on the second RC region 703 are transferred being advanced by one pitch of the pixel 701 with respect to the charges on the first RC region 702 in synchronism with one another. Accordingly, the drive pulse signal Ca shown in FIG. 7 corresponds to the drive pulse signal 8b shown in FIG. 5D, and the drive pulse signal Cb shown in FIG. 7 corresponds to the drive pulse signal 8a shown in FIG. 5C, respectively.
The charge transfer device shown in FIG. 7 operates in quite the same way as with the case of the charge transfer device shown in FIG. 3, although the shapes of the electrodes are different between both.
In the conventional charge transfer device of two-line read structure as described above, it is possible to double the pitch of the register portion as compared with the conventional device of single-line read structure. Further, in the case of the device of structure of three or more lines, it is possible to increase the pitch of the register portion three times or more according to the number of lines. Accordingly, the charge transfer device of multi-line read structure is effective, when the high density charge transfer device in which the pitch of the pixels is small is required to be manufactured.
In the above-mentioned conventional charge transfer device of multi-line structure, however, the TC region 802 for transferring charges between registers 702 and 703 must be formed additionally. In this case, since the width of TC region 802 tends to be limited and thereby narrowed due to the layout of other portions (e.g., electrode wiring and channel separating regions must be formed), there exists a problem in that potential barriers X (see FIG. 6A) are produced at the outlet portions of the first RC region 702 on the side of the TC region 802 and thereby transfer of the charges e2 is obstructed by the presence of the potential barriers X, thus causing the charges to be not transferred and thereby to remain.
In addition, although being suitable for high density device, the multi-line structure raises another problem in that it is difficult to form the TC region 802 according to the pixel pitch from the layout standpoint.